The present invention relates to a semiconductor memory device, such as a dynamic random access memory (DRAM), of alternately-activated open-bit line architecture, and more particularly to a method of driving dummy word lines for cancellation of noises to be generated when word lines and bit lines are activated.
FIG. 1A shows a prior art DRAM of alternately-activated open bit-line architecture as disclosed in 1991 the Institute of Electronics, Information and Communication Engineers Spring National Convention Records C-660. FIG. 1B is an enlarged detail of the DRAM shown in FIG. 1A. Referring to FIG. 1A, the DRAM has differential sense amplifiers SA (only three of which are shown) arranged in a row, and pairs of bit lines connected to the sense amplifiers SA. Two pairs of bit lines B0 and /B0, B1 and /B1 extend outwardly from opposite sides of each sense amplifier SA. Memory cells MC are disposed at intersections between the alternate bit lines B0, B1, /B0, /B1 and word lines W1, W2, W3, W4. In reading operation, when the word line W1, for example, is activated, the alternate bit lines B0 are activated by a signal (storage charge) in the memory cells MC connected to the word line W1. At this time, electric potentials on the bit lines B1 are fixed, and therefore interference noise between neighboring bit lines is greatly reduced.
Referring to FIG. 1B, there are also shown dummy cells DC and dummy word lines DW1, . . . , DW4. Such components are often employed not only in a DRAM of open bit-line architecture but also in a common DRAM. The dummy cells DC and the dummy word lines DW1, . . . , DW4 have utterly the same constructions as those of the memory cells MC and the word lines W1, . . . , W4 respectively, inclusive of parasitic capacitance. When a signal is read out on the bit lines B0, for example, from the corresponding memory cells MC, various noises similar to those generated on the bit line B0 are made to be generated on the counterpart bit line /B0 as well. Various noises occurring during the data reading operation are thereby canceled and the intensity of the signal is increased.
In the above example, the sense amplifiers SA are arranged in a row at a pitch equivalent to twice the bit line pitch. However, when the integration scale exceeds the level of a 64 Mbit DRAM (wherein the bit line pitch is about 1.0 .mu.m), it is difficult to arrange the sense amplifiers SA in a width corresponding to twice the bit line pitch. This is because channel lengths of transistors constituting each sense amplifier SA and the size of diffusion regions cannot be reduced in conformity to a scaling rule since the sensitivity of each sense amplifier SA is required to be maintained at a certain high level. In more detail, when the channel lengths of the transistors constituting each sense amplifier SA are reduced, a difference takes place between the paired transistors in effective channel length and/or threshold voltage due to a scatter in fabrication process of the transistors. On the other hand, when the diffusion regions are dimensionally reduced, a difference takes place between the load capacitances of the sense amplifiers SA. Those differences are major factors of the reduction of the sensitivity of each sense amplifier SA.
For the above reasons, the prior art arrangement cannot be used for high density DRAMs.
In order to solve this problem, the present inventor has designed an improved DRAM of alternately-activated open bit-line architecture. The arrangement of the DRAM is shown in FIG. 2. In the DRAM shown in FIG. 2, differential type sense amplifiers SA are arranged in a staggering manner. Two bit lines extend from either side of each sense amplifier, and a plurality of word lines (only two of which are shown by WL1 and WL2) and two dummy word lines (DWL1 and DWL2) intersect the bit lines positioned between the rows of the sense amplifiers. Memory cells MC are provided at intersections between the bit lines and the word lines WL1, WL2 and dummy memory cells DC are provided at intersections between the bit lines and the dummy word lines DWL1, DWL 2 so that cell array blocks (four ow which are shown by MB0, MB1, MB2, MB3) are provided between the rows of the sense amplifiers SA. According to this arrangement, the sense amplifiers SA in each row can be arranged at a pitch equivalent to at least four times the bit line pitch. Accordingly, even though the bit line pitch is reduced, a relatively large area can be assured for each sense amplifier SA (more specifically, for the channel length and/or diffusion area of each transistor). As a result, it is possible to increase the packing density while keeping high the sensitivity of each sense amplifier.
However, the inventor has found that this improved DRAM has the following drawbacks.
For example, when a word line WL1 connected to the cell array block MB2 is activated to select memory cells MC provided at the intersections between the word line WL1 and the bit lines BL0, BL2, BL4, BL6, for example, two dummy word lines DWL2 connected to the neighboring cell array blocks MB1 and MB3 respectively must be activated at the same time. This is because bit lines /BL0, /BL2, /BL4, /BL6 being counterparts of the bit lines BL0, BL2, BL4, BL6 are arranged alternately in the neighboring memory cell blocks MB1 and MB3. Thus, this arrangement requires a complicated operation and circuit design for driving the dummy word lines. Furthermore, one dummy word line located in a certain cell array block can be a counterpart of the word lines located in different two cell array blocks on both sides of the certain cell array block. For instance, the dummy word line DWL1 provided in the cell array block MB2 is activated when memory cells MC in either of the neighboring cell array blocks MB1 and MB3 are selected. This also complicates the operation and circuit design for driving the dummy word lines. FIG. 3 shows waveforms of drive signals for the word lines WL (WL1, WL2) and the dummy word lines DWL (DWL1, DWL2). As shown in FIG. 3, both the word lines and the dummy word lines assume a potential of ground GND when not selected and an elevated potential VBST higher than a potential of a power supply when selected.